(1) Field of the Invention
The present invention relates to a method and an apparatus for analyzing power consumption. More particularly, the present invention relates to a method and an apparatus for analyzing power consumption of a semiconductor integrated circuit.
(2) Description of the Related Art
In design of a system Large Scale Integrated circuit (LSI), it is necessary to confirm before the manufacture that power consumption of the whole chip is a limit value or less and accordingly, power consumption analysis with high accuracy must be performed. Many apparatuses and methods for calculating the power consumption have been developed.
For example, there is known a method of measuring an operating rate of a combinational circuit or a register (the number of changes of a signal) using a logic simulation and calculating the power consumption from a current equation of a load carrying capacity and a basic circuit. Further, there is known a power consumption analysis method using hardware such as an Field Programmable Gate Array (FPGA).
In addition, various types of emulator devices for performing a logic simulation at a high speed using hardware are commercially available. Examples of the emulator devices include the Palladium system by Cadence Design Systems, the System Explorer system by Aptix Corporation and the Celaro emulator by Mentor Graphics Corporation.
Further, there is known a gated clock technique in which when a circuit block including a combinational circuit and a register does not operate, a clock input to the register within the circuit block is stopped in order to reduce power consumption.
In the above-described conventional power consumption analysis methods, an operating rate (an operating rate per unit time) of all the gate circuits of a chip must be added in order to evaluate the power consumption of the whole chip.
Accordingly, in the conventional power consumption analysis methods, when an analysis object is a large-scale circuit including, for example, tens of millions of gate circuits, the data amount of logic simulation results stored for adding the operating rate becomes enormous. As a result, a longer data collection or processing time is required and it takes a long time to analyze the power consumption.